1. Field of the Invention
The present invention relates to an automated wiring pattern layout method using CAD; a semiconductor integrated circuit, which is manufactured through this automated layout method; and storage media recorded with an automated layout program.
2. Description of the Related Art
Accompanying the increased large scale of circuits through progress in LSI technologies, the amount of circuit layout design and the mask design process have become immense. Therein, layout design is being performed through computer aided design (CAD), which is a logical design method capable of making effective use of a computer.
Accompanying the miniaturization of circuits in recent years, besides wiring resistance, the resistance of a VIA contact connecting differing layers of wiring to each other is an important element which must be considered when deciding chip performance. The mask for VIA contacts has a rectangular-shaped contact plane pattern with an aspect ratio (ratio of long edge to short edge) of nearly 1, and is the most miniature pattern in the various wiring masks. In addition, it is the region having a relatively small lithography process margin, where that region determines the accuracy of the lithography process. As one method of guaranteeing accuracy of such a post-exposure transferred pattern of such a minute shape, there is a method which shortens the wavelength of the light source used in photolithography; however shortening of the wavelength of the exposure light cannot always keep pace with device miniaturization, which increases every year.
Therefore, it has become important to have VIA design, which secures as much via contact cross-sectional area as the accuracy of the lithography can guarantee, and which uses current exposure apparatuses to the furthest extent possible.
In addition, with miniaturization processes of late, in order to compensate for the finished dimensions around the post-exposure processing VIA, layout pattern data correction is performed by conducting optical corrective processing called optical proximity correction (OPC). More specifically, as shown in FIG. 1A, with a CAD-based layout pattern, a VIA contact pattern 1301 is set at the end portion where two wiring patterns M1 and M2 intersect; however, if exposure is actually performed using a mask produced based on this layout pattern, as shown in FIG. 1B, the VIA contact pattern 1303 transferred onto the wafer is reduced. This reduction phenomenon is especially prominent in cases where the process margin for the lithography determining the mask process accuracy is small; thus the pattern transferred upon the wafer is remarkably reduced in comparison with the designed data. As a result, not only does the VIA resistance increase deteriorating the circuit performance, but breakage occurs due to weakened electromigration resistance.